2.1 Segment 0 to 14
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2.1 Segment 0 to 14
Section titled “2.1 Segment 0 to 14”The address map of segments 0 to 14 describes the allocation of the SRI/SPB address space. The segments contain CPU local memory, Program Flash, Data Flash, external memory interfaces, and various control registers.
Segment Overview
Section titled “Segment Overview”| Segment | Address Range | Size | Description |
|---|---|---|---|
| 0 | 0000 0000H - 0FFF FFFFH | 256 Mbyte | Reserved (virtual address space) |
| 1 | 1000 0000H - 100B FFFFH | - | CPU5 DSPR, DCACHE, DTAG |
| 2 | 2000 0000H - 2FFF FFFFH | - | Reserved |
| 3 | 3000 0000H - 300B FFFFH | - | CPU4 DSPR, DCACHE, DTAG |
| 4 | 4000 0000H - 400B FFFFH | - | CPU3 DSPR, DCACHE, DTAG |
| 5 | 5000 0000H - 500B FFFFH | - | CPU2 DSPR, DCACHE, DTAG |
| 6 | 6000 0000H - 600B FFFFH | - | CPU1 DSPR, DCACHE, DTAG |
| 7 | 7000 0000H - 700B FFFFH | - | CPU0 DSPR, DCACHE, DTAG |
| 8 | 8000 0000H - 8FFF FFFFH | 256 Mbyte | Program Flash, EBU, BROM |
| 9 | 9000 0000H - 9011 FFFFH | - | LMU |
| 10 | A000 0000H - A8FF FFFFH | 144 Mbyte | Program Flash, EBU, Erase Counters, PFI |
| 11 | B000 0000H - B043 FFFFH | - | LMU, DAM, TRAM |
| 12 | C000 0000H - CFFF FFFFH | - | Reserved |
| 13 | D000 0000H - DFFF FFFFH | - | Reserved |
| 14 | E000 0000H - EFFF FFFFH | - | Reserved |
Segment 0
Section titled “Segment 0”Segment 0 is a reserved virtual address space. If an SPB access to 0000 0000H occurs, the SPB BCU generates a bus error.
Segment 11
Section titled “Segment 11”This memory segment allows non-cached access to LMU and to EMEM.
Segment 12, 13
Section titled “Segment 12, 13”These segments are reserved.
Segment 14
Section titled “Segment 14”This segment is reserved.
Segment 15
Section titled “Segment 15”The lower 128 Mbyte is SPB address space and the upper 128 Mbyte is SRI address space. See Table 40 for details.
[Figure 16: Segment F Structure — image not included]