1.3.2 Feature List

此内容尚不支持你的语言。

Eight hardware breakpoints for TriCore, based on instruction or data address
Unlimited number of software breakpoints (DEBUG instruction)
Trigger generated by the access to a specific bus address by any bus master
Peripheral trigger and trace with OCDS Trigger Bus (OTGB)
- Peripherals provide vectors (Trigger Sets) of their most interesting signals.
- Signals can be routed to trigger pins.
- Flexible tracing of signal vectors from one to three peripherals in parallel
Dedicated interrupt resources to handle debug events, both local inside the CPUs (breakpoint trap, software interrupt) and global (triggered by Cerberus)

Run/stop and single-step execution independently for each CPU
Run/stop and time-step execution of the complete device using the Trigger Switch
Automatic suspension of CPU associated watchdogs and system timers if the CPU is halted by the tool
All kinds of reset can be requested using only the tool interface
Halt-after-Reset for repeatable debug sessions
Tool access to all SFRs and internal memories independent of the CPUs
Bus priority of Cerberus can be chosen dynamically to minimize real-time impact
Up to 8 package pins can be used optional as with Trigger In/Out (TGI/TGO)
Central OCDS Trigger Switch (OTGS) with 7 independent Trigger Lines
Central Suspend Switch using up to three Lines of the Trigger Switch infrastructure
Access to all OCDS resources for CPUs themselves for debug tools integrated into the application code
Triggered Transfer of data for simple variable tracing
A dedicated trigger bank (TRIG) with 96 independent status bits
Fault and stress injection for testing the robustness of a system

Several options exist for the communication channel between tools and devices:

DAP and JTAG are clocked by the tool
Two pin DAP protocol for long connections or noisy environments
Three pin DAP Unidirectional Mode for off-chip transceiver integration (e.g. LVDS)
Three pin DAP Wide Mode for high bandwidth needs
Four pin DAP Unidirectional Wide Mode for off-chip transceiver integration with high bandwidth needs
DAP bit clock can have any frequency up to 160 MHz
15 MByte/s for block read or write, 25–30 MByte/s in Wide Mode and Unidirectional Wide Mode
Optimized random memory accesses (read word within 0.5 μs at 160 MHz)
CAN (plus software linked into the application code) for embedded purposes with lower bandwidth requirements
DAPE can be used in parallel to DAP to connect a second tool for Emulation Devices
Four pin JTAG (IEEE 1149.1) for standard manufacturing tests
Lock mechanism to prevent unauthorized tool access to application code
Hot attach capability
Infineon standard DAS (Device Access Server) implementation
DAP over CAN Messages (DXCM)

To efficiently locate and identify faults after integration:

Boundary Scan (IEEE 1149.1) via JTAG or DAP
SSCM (Single Scan Chain Mode) for structural scan testing of the chip itself
DXCPL (DAP over CAN Physical Layer) via CAN pins (AP32264)

Note: Boundary scan is possible also for locked devices. The security barrier is within CERBERUS.