1.2 System Architecture of the AURIX TC3xx Platform

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1.2 System Architecture of the AURIX™ TC3xx Platform

The AURIX™ TC3xx Platform is a family of high-performance microcontrollers with multiple TriCore CPUs, program and data memories, buses, bus arbitration, interrupt system, DMA controller, and a powerful set of on-chip peripherals. The AURIX™ TC3xx Platform is designed to meet the needs of the most demanding embedded control systems applications where the competing issues of price/performance, real-time responsiveness, computational power, data bandwidth, and power consumption are key design elements.

Within the AURIX™ TC3xx Platform, all peripheral units are connected to the TriCore CPUs/system via a System Peripheral Bus (SPB) and a Shared Resource Interconnect (SRI).

The TriCore processor architecture combines three powerful technologies within one processing unit:

Reduced Instruction Set Computing (RISC) processor architecture
Digital Signal Processing (DSP) operations and addressing modes
On-chip memories and peripherals

DSP operations and addressing modes provide the computational power necessary to efficiently analyse complex real-world signals. The RISC load/store architecture provides high computational bandwidth with low system cost.

Additional high-level features:

Multicore Architecture
Efficient memory organization: instruction and data scratch memories, caches, and local flash banks
Serial communication interfaces – flexible synchronous and asynchronous modes
Multiple channel DMA Controller
Flexible interrupt system – configurable interrupt priorities and targets
Hardware Security Module
Flexible CRC Engine
General-purpose timers
High-performance on-chip buses
On-chip debugging and emulation facilities
Flexible interconnections to external components
Flexible power-management

ADAS or Extended features available in some products:

Camera Interface
Radar Interface
Extended Memory
ADAS Signal Processing Unit