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infineon
英飞凌文档
usermanual
aurix_tc3xx
AURIX TC3XX 用户手册
chapter-01-introduction
1 Introduction
1.1.1 Related Documentations
1.1.2 Text Conventions
1.1.3 Family Specification and Appendix
1.1.4 Register and Memory Address Documentation
1.1.5 Reserved, Undefined, and Unimplemented Terminology
1.1.6 Register Access Modes
1.1.7 Register Reset Documentation
1.1.8 Abbreviations and Acronyms
1.1 About this Document
1.2.1 AURIX TC3xx Platform High End – TC39x
1.2.2 Family Overview
1.2.3.1 Encoding of the Product Name
1.2.3.2 Emulation Devices
1.2.3.3 TC32x
1.2.3.4 TC39x With Feature Package P
1.2.3 Variants
1.2.4 Revision History
1.2 System Architecture of the AURIX TC3xx Platform
1.3.1 Introduction
1.3.2 Feature List
1.3.3 Family Overview
1.3.4 Tool Interface Recommendations
1.3.5 Debug Access Server (DAS)
1.3.6 Revision History
1.3 On-Chip Debug Support (OCDS)
1.4.1 Block Diagram
1.4.2 Feature List
1.4.3 Comparison to AURIX Emulation Devices
1.4.4.1 TMUX Setting Options
1.4.4.2 Trace Source Multiplexer in CPU Subsystem (TCMUX)
1.4.4.3 Parallel Trace Use Cases
1.4.4 Trace Source Multiplexer
1.4.5 DAP ED Interface (DAPE)
1.4.6 Revision History
1.4 Emulation Device (ED)
1.5.1 Overview
1.5.2.1 Configuration Parameters
1.5.2.2 Initial Device Configuration for SOTA
1.5.2.3 Runtime SWAP Configuration
1.5.2 Functional Description
1.5.3 Safety
1.5.4 Security
1.5.5 Revision History
1.5 Software over the Air (SOTA)
chapter-02-memory-maps
2 Memory Maps (MEMMAP)
2.1.1 CPU Local Memory Address Map
2.1.2 Program Flash and External Bus
2.1.3 LMU, DAM, EMEM and Trace Memory
2.1.4 Segment 15 Address Map
2.1 Segment 0 to 14
2.2 Alternate Address Maps for SOTA
2.3 Functional Description
2.4 Memory Map Revision History
nxp
NXP文档
st
ST文档
stm32
STM32文档
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Infineon Documentation
Section titled “Infineon Documentation”
Welcome to Infineon documentation.