1.1.8 Abbreviations and Acronyms

Table 7: Abbreviations and Acronyms

Acronym	Description
ADAS	Advanced Driver Assistance System
ADC	Analog-to-Digital Converter
ALU	Arithmetic and Logic Unit
ASCLIN	Asynchronous/Synchronous Serial Controller with LIN
BBB	Back Bone Bus
BCU	Bus Control Unit
BROM	Boot ROM & Test ROM
CAN	Controller Area Network
CIF	Camera (and ADC) Interface
CCU	Clock Control Unit
CPU	Central Processing Unit
CRC	Cyclic Redundancy Code
CSA	Context Save Area
CSFR	Core Special Function Register
CCU6	Capture Compare Unit 6
DAM	Default Application Memory
DAP	Device Access Port
DAS	Device Access Server
DPI	Direct Processor Interface (to Local Flash Bank)
DCACHE	Data Cache
DFLASH (or DF)	Data Flash Memory
DLMU	Direct-connected Local Memory Unit
DMA	Direct Memory Access
DMBI	Data Memory Bus Interface
DMI	Data Memory Interface
DMU	Data Memory Unit
DRLB	Data Read Line Buffer
DSPR	Data Scratchpad RAM
EBU	External Bus Interface
ECC	Error Correction Code
ED	Emulation Device
EDSADC	Enhanced Delta-Sigma Analog to Digital Converter
EVADC	Enhanced Versatile Analog-to-Digital Converter
EMI	Electro-Magnetic Interference
ERAY	Flexray Controller
EtherMAC	Ethernet Media Access Controller
EVR	Embedded Voltage Regulator
FCE	Flexible CRC Engine
FCOMP	Fast Comparator
FM-PLL	PLL with Frequency Modulation support
FPI	Flexible Peripheral Interconnect (Bus protocol)
FPU	Floating Point Unit
FSM	Finite State Machine
GPIO	General Purpose Input/Output
GPT12	General Purpose Timer 12
GTM	Generic Timer Module
HSM	Hardware Security Module
HSPDM	High Speed Pulse Density Modulator
HSSL	High Speed Serial Link
I2C	Inter-Integrated Circuit Controller
I/O	Input / Output
IOM	I/O Monitor Unit
IR	Interrupt Router
JTAG	Joint Test Action Group = IEEE1149.1
LMU	Local Bus Memory Unit
MBIST	Memory Build In Self Test
MMU	Memory Management Unit
MSB	Most Significant Bit
MSC	Micro Second Channel
MTU	Memory Test Unit
MCMCAN	CAN controller
NC	Not Connected
NMI	Non-Maskable Interrupt
NVM	Non Volatile Memory
OCDS	On-Chip Debug Support
OVRAM	Overlay Memory
PLL	Phase Locked Loop
PCACHE	Program Cache
PD	Production Device
PFI	Program Flash Interface
PFLASH (or PF)	Program Flash Memory
PMBI	Program Memory Bus Interface
PMI	Program Memory Interface
PMS	Power Management System
PSI5	Peripheral Sensor Interface
PSI5-S	Peripheral Sensor Interface with Serial Interface to Phy
PSPR	Program Scratchpad RAM
QSPI	Queued SPI Controller
RAM	Random Access Memory
RCU	Reset Control Unit
RIF	Radar Interface
RISC	Reduced Instruction Set Computing
SBCU	System Peripheral Bus Control Unit
SCU	System Control Unit
SCR	Standby Controller
SENT	Single Edge Nibble Transmission
SFR	Special Function Register
SMU	Safety Management Unit
SPB	System Peripheral Bus (based on FPI protocol)
SPU	Signal Processing Unit
SPD	Single Pin DAP
SPI	Synchronous Serial Controller
SRI	Shared Resource Interconnect
SRAM	Static Data Memory
SRN	Service Request Node
STM	System Timer
SWD	Supply Watchdog
TC1.6.2P	TriCore CPU TC1.6.2P
UCB	User Configuration Block
WDT	Watchdog Timer
XBar, XBar_SRI	Cross Bar Interconnect, based on the Shared Resource Interconnect protocol